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IC Packaging and SiP Community

 
Build Components Quickly and Easily with Pre-Defined Escape Routing Using Cadence 16.6 IC Packaging Tools
By Jeffrey Gallagher on June 02, 2014
When it comes to designing a dense flip-chip die - or even defining a BGA for a complex substrate - the ability to efficiently fan out the pins in the fewest possible layers is paramount. Get this wrong, and you could end up needing additional layers... Read more »
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Add a View of Your Package Substrate in Your IC Layout Tool for Maximum Design Context with Cadence 16.6 SiP Layout
By Jeffrey Gallagher on May 01, 2014
We have all heard about co-design, how it is going to get us to market on time, reduce our layer counts, and give us the ability to trade off design decisions at different layers of the system substrates. If you're reading this blog, you almost certainly... Read more »
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OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014
By Team Allegro on April 08, 2014
The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. (See the complete two-day agenda .) Track 6, IC Packaging/SI, PI, featured customer papers on co-design as well as signal and... Read more »
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