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IC Packaging and SiP Community

 
OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014
By Team Allegro on April 08, 2014
The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. (See the complete two-day agenda .) Track 6, IC Packaging/SI, PI, featured customer papers on co-design as well as signal and... Read more »
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Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2014
By Team Allegro on March 28, 2014
The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. For the complete two day agenda, click here . Track 6, the IC Packaging/SI, PI featured customer papers on co-design as well... Read more »
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Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6 IC Packaging Layout Tools
By Jeffrey Gallagher on March 26, 2014
To maximize yield and achieve optimum quality of your final, manufactured IC package substrate, we all want to balance the metal coverage across different layer - and region - pairings of your package layout. But, just how do you go about doing that with... Read more »
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