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	What's Good About PCB SI Signal Integrity Application Mode? It’s in the 16.5 Release! By Gerald "Jerry" Grzenia on January 31, 2012 In release 16.0, the concept of Application Modes was introduced. These application modes are used to set up the tool for specific tasks. The existing applications are General Edit, Etch Edit, and Placement. In 16.5, the Signal Integrity (SI) application... Read more » Comments (0) Filed under: PCB Layout and routing, PCB design, Allegro, SI, PCB, PCB SI, layout, PCB Signal integrity, High Speed, Allegro 16.5, signal integrity, 16.5, application mode

	What's Good About APD’s Die Abstract Libraries? You’ll Need the 16.5 Release to See! By Gerald "Jerry" Grzenia on January 24, 2012 In System in Package (SiP) 16.3, the co-design die flow introduced the distributed co-design flow concept, where there is no direct interaction with I/O Planner. Die information flowing between Encounter and SiP Layout is done via a die abstract. In flows... Read more » Comments (0) Filed under: PCB design, Allegro, Librarians, APD, IC Packaging and SiP Design, IC Packaging, PCB, layout, "PCB design", Digital SiP design, Library, design, SPB16.5, Allegro 16.5, PCB design", packaging, die abstract compare, Allegro Package Designer, IC/package co-design, CML, die abstracts

	What's Good About Allegro GRE Constraint Region Support? It’s in the 16.5 Release! By Gerald "Jerry" Grzenia on January 18, 2012 The 16.5 Global Route Environment ( GRE ) now allows or prohibits tuning in constraint regions. This functionality was designed to help PCB designers prevent delay routing in constraint regions. This is generally desirable as the space is so tight in... Read more » Comments (0) Filed under: PCB Layout and routing, PCB design, Allegro PCB Editor, Allegro, PCB Editor, PCB, layout, "PCB design", GRE, routing, SPB16.5, Allegro 16.5, constraint region

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