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PCB Design Community

 
DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques
By Team Allegro on August 14, 2014
The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit serial link interfaces are now starting to be applied... Read more »
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What's Good About Allegro DEHDL Net Renaming? The Secret's in the 16.6 Release!
By Gerald "Jerry" Grzenia on August 12, 2014
Just a brief post this week to mention a new capability for Allegro Design Entry HDL (DEHDL) that was made available in the 16.6-QIR4 release. You can now employ net renaming without loss of data: All instances of the net will be renamed to a new name... Read more »
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What's Good About Allegro PCB Editor Multiple Constraint Region Assignments? 16.6 Has It!
By Gerald "Jerry" Grzenia on July 28, 2014
Just a short post today. In the 16.6 Allegro PCB Editor release, multiple region shapes can now be assigned to a single region constraint object. Using the General Edit Application mode, pre-select multiple region shapes, then use the context-sensitive... Read more »
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