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Silicon Signoff and Verification

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	DAC DFM Coalition - Do You Work On Sunday Afternoons? By Wilbur Luo on July 14, 2010 It was a sunny, Sunday afternoon in Anaheim (across from Disneyland). That combination of weather and entertainment didn't sway a group of 35 engineers from participating in the DFMC (Design for Manufacturability Coalition) Workshop at DAC 2010. On... Read more » Comments (0) Filed under: Litho-aware design, CMP-aware design , Chip Optimization, Design for yield, Silicon Signoff and Verification, strategy for design-for-yield, foundry, EDA, mixed-signal, DAC, DFM

	Tidbits From TSMC Q209 Earnings Call - 40nm Yield By Wilbur Luo on August 07, 2009 Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM... Read more » Comments (1) Filed under: Litho-aware design, CMP-aware design , Physical verification, Chip Optimization, Design for yield, Silicon Signoff and Verification

	Moore no More By Christopher Clee on April 10, 2009 "The number of watchmen required to watch the watchmen watching the watchmen tends to double every 18 months". This gem is Alan Moore's law, posted years ago by some wag in response to an Intel article on geek.com . This has, of course,... Read more » Comments (1) Filed under: EDA, Moore's law, intel, mixed-signal, advanced node

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