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 Cadence Member: About tpylant 

tpylant   | 2030 points
Austin, TX
Design and Verification Core Comp
Member since: July, 2008
Bio I started my career in 1984 doing board design for F-16 avionics and then moved to Compaq Computer in 1988 where I supported the use of design and verification tools for ASIC development. In 1992, I joined Cadence to continue that role as an Applications Engineer. I am currently working in the Design and Verification Core Comp team in support of SystemVerilog, assertion-based, and low-power verification. I have also published several papers in these areas and been a reviewer for SystemVerilog for Verification and Step-by-Step Functional Verification with SystemVerilog and OVM. Academic Background Texas A&M University EET 1980 – 1984
University of Houston MBA 1989 – 1991

Organization Affiliations No profile info has been provided Community Interests Functional Verification
Personal Interests No profile info has been provided Publications Other Online:  www.linkedin.com/pub/8/355/752
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Create a Sine Wave Generator Using SystemVerilog
by tpylant