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 Cadence Member: About Adam Sherilog 

Adam Sherilog   | 1785 points
Chelmsford, MA
Member since: June, 2008
Search for posts by Adam Sherilog
Bio I market the UVM, multi-language verification, and low-power simulator for Cadence, tapping 21 years of experience in verification and software engineering including roles in marketing, product management, applications engineering, and R&D. With eight consecutive Boston Marathons run on the Boston Children’s Hospital Marathon Team, I'm always ready to see who has the fastest verification on the planet!

Look for me in the 2014 Boston Marathon. Boston Stands As One. Academic Background * MS EE from the University of Rochester, with research published in the IEEE Transactions on CAD
* BS EE and BA CS from SUNY Buffalo
 Organization Affiliations Accellera VIP TSC Secretary Community Interests System Design and Verification
Functional Verification
 Personal Interests Running/racing, hiking with my kids, biking Publications Blog:  Tweet: @SeeAdamRun
 		My Friends

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
by Adam Sherilog on May 07, 2013 12:41 PM

IBM and Cadence Collaboration Improves Verification Productivity
by Adam Sherilog on February 13, 2013 11:00 AM

Your First Low-power Verification Project - Webinar
by Adam Sherilog on October 11, 2012 10:00 AM