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Logic Design Community

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	8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com By David Stratman on June 20, 2011 It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design... Read more » Comments (0) Filed under: Logic synthesis, Low power , Logic Design, CPF, power management, Common Power Format, Synthesis, RTL, encounter, RTL compiler, cadence, synopsys, rc, methodology, DAC, Digital, Digital End-to-End, design comipler, DC, DeepChip, Cooley

	Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line By Kenneth Chang on February 07, 2011 Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments... Read more » Comments (0) Filed under: Logic Design, conformal, Conformal ECO, encounter, ECO, Digital End-to-End, ECO Designer, ECOs

	New Era Of SoC Design – Still Enabled By Logic Designers By Jack Erickson on July 08, 2010 If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that are networked... Read more » Comments (0) Filed under: Synthesis, RTL compiler, C-to-Silicon, TLM, EDA360, Silicon Realization, SoC Realization

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