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Logic Design Community

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	When Will We Move From RTL to TLM? I Need to Know! By Jack Erickson on March 08, 2010 My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point... Read more » Comments (0) Filed under: Logic Design, Synthesis, RTL, RTL compiler, C-to-Silicon, TLM

	What Can We Learn From The iPad About Chip Design? By Jack Erickson on February 02, 2010 You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT... Read more » Comments (0) Filed under: Logic Design, ARM, system design, IP, Jack Erickson, Apple, Imagination, software, iPad

	RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition! By Jack Erickson on January 25, 2010 I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize... Read more » Comments (0) Filed under: Logic Design, Synthesis, RTL compiler, timing constraints, C-to-Silicon, Physical Synthesis, TLM

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