Home > Community

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Logic Design blog (individual posts).

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Logic Design Community

Blog
Forum
Resources

	Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose By Kenneth Chang on November 27, 2012 Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via... Read more » Comments (0) Filed under: cadence, conformal, encounter, Encounter Test, front end, front-end design, front-end summit, Kenneth Chang, Logic Design, RTL compiler

	Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler By Sumeet Aggarwal on August 07, 2012 Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true... Read more » Comments (0) Filed under: boundary optimizations, fixing timing violations, Functional Verification, Logic Design, optimizations, rc, RTL compiler, Synthesis

	Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs) By Sumeet Aggarwal on July 24, 2012 A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis,... Read more » Comments (0) Filed under: ATPG, conformal, customer enablement, EDI, Encounter Test, Incisive, Incisive Enterprise Simulator, Incisive Unified Simulation, LEC, Logic Design, Logic synthesis, RAKs, rapid adoption kits, RTL compiler, Synthesis, Test, Verification

View older posts »

Visit the Logic Design forum »

There are 35 guest(s) and 0 member(s) online:

Most Active Users

Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

Email

Share

Subscribe

Contact Us

Logic Design Community