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Functional Verification Community

 
Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More
By Chinmay Banerjee on August 13, 2014
The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than verification. Today, with the increase in number of performance... Read more »
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Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing Cadence Online Support, 2Q 2014
By Sumeet Aggarwal on July 28, 2014
Cadence Online Support, http://support.cadence.com , provides access to support resources including an extensive knowledge base, access to software updates for Cadence products, and the ability to interact with Cadence Customer Support. In the June release... Read more »
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Implementing User-Defined Register Access Policies with vr_ad and IPXACT
By Team Specman on July 02, 2014
The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the register e-file can be automatically generated from it... Read more »
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