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Functional Verification Community

 
Objection Mechanism Synchronization Between SystemVerilog and e Active Verification Components
By Team Specman on September 02, 2014
What happens when you have two verification components (for example one implemented in e and the other in System Verilog) and one of the frameworks drops its last TEST_DONE objection?... Read more »
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Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina Display
By Axel Scherer on September 02, 2014
The Retina display in the Apple MacBook Pro has much more value than I originally expected. As similar observatiom is being made about the Incisive debug Analyzer.... Read more »
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Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More
By Chinmay Banerjee on August 13, 2014
The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than verification. Today, with the increase in number of performance... Read more »
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