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 Defining a string parameter in a systemverilog model as a design variable 

Last post Fri, Jan 24 2014 4:49 PM by Soner. 2 replies.
Started by Soner 21 Aug 2013 05:29 PM. Topic has 2 replies and 7014 views
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  • Wed, Aug 21 2013 5:29 PM

    • Soner
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    Defining a string parameter in a systemverilog model as a design variable Reply

    Hi, I have a systemverilog module with a string parameter:

    parameter string filename = "default_name"; 

    When I instantiate this module and edit its object properties, I see the filename property. Whatever I write into this field is passed as a string to the module. Is it possible to define a design variable (which value I can control in ADE) and pass this design variable to this field? 

    The motivation is to be able to provide a unique filename in a parametric analysis. Otherwise, the file will be overwritten for each simulation.

     

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    • Post Points: 20
  • Tue, Aug 27 2013 10:04 PM

    Re: Defining a string parameter in a systemverilog model as a design variable Reply

    I think so - although I've not tested this. You'd have to ensure that the parameter is defined in the CDF as parseAsCEL=yes though. If that doesn't work, please contact customer support (I'm assuming AMS is the simulator).

    KInd Regards,

    Andrew.

    • Post Points: 20
  • Fri, Jan 24 2014 4:49 PM

    • Soner
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    Re: Defining a string parameter in a systemverilog model as a design variable Reply

    Hi Andrew,

    Here is a workaround: 

    1) Ensure that the parameter is defined in the CDF as parseAsCEL=yes

    2) Edit object properties of the instance, type pPar("myVariable")

    myVariable shows up as a design variable in ADE XL. Is it possible to make step #1 above automatic, just like parameters of type real?

    Regards,

    Soner Yaldiz 

    • Post Points: 5
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Started by Soner at 21 Aug 2013 05:29 PM. Topic has 2 replies.