I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation. However, how to get the aging model file (which describes, e.g., Vth shift and mobility degradation over time for the individual devices under stress) needed by RelXpert? I have access to design kits from TSMC, IBM, and STM (65nm, 90nm, 0.13um, 0.18um). Is the aging model file provided with in the design kits for this technology? If so, how to find it? Or, is it only available by contacting the foundry?
Besides, Cadence shows that RelXpert can be used with Spectre with in ADE in IC61x version.https://www.cadence.com/cdnlive/library/Documents/2009/NA/100509%20-%20Track1-3%20-%20Xiao%20Wang%20-%20Cadence_Final.pdf
I have tried with IC613, but there is no “RelXpert”item under “Simulation” in ADE, as shown in the linked pdf above. So, how to get access to RelXpert, just like the way shown in that pdf?
Besides, I know that there is a simulator named “Eldo” from Mentor can perform aging simulation. IBM cmos56nm technology (i.e. STM 65nm) provides the aging model file that can be used in Eldo. The manual of STM 65nm shows that Eldo was selected and used within ADE. However, I can not find Eldo in the simulator menu in ADE. I guess this is because Eldo is not loaded into Cadence when it is started. So, how to get access to Eldo in ADE?
Thank you very much!