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 Forums 

Cadence Technology Forums
Forum NameTopicsRepliesLast Post
    Hardware/Software Co-Development, Verification and IntegrationModerator: Frank Schirrmeister232509PSpice Simulation with Rogowsk ...
By: Mescheltana
30 Jul 2014 02:04 AM
    Functional VerificationModerator: Adam Sherer12043821Re: How to suppress the warnin ...
By: muffi
30 Jul 2014 09:04 PM
    Functional Verification Shared CodeUpload your code here. Please give a brief summary of how to use it. 56152Re: Shell Script rc
By: MStarilov
03 Jul 2014 07:25 AM
    Logic Design Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
5441550Re: LEC debug points report ge ...
By: sogold
22 Jul 2014 07:53 PM
    Digital ImplementationDesign Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
17035339Parasitic Extraction including ...
By: salmancmosis
30 Jul 2014 12:53 AM
    Custom IC DesignModerator: Andrew Beckett.313812783Re: VerilogA compiler
By: Sali
30 Jul 2014 12:50 PM
    Custom IC SKILLModerator: Andrew Beckett.239010808How to display a list content ...
By: Charley Chen
30 Jul 2014 07:38 PM
    RF DesignModerator: Andrew Beckett.4771924Re: Simulating Phase noise at ...
By: Andrew Beckett
30 Jul 2014 01:24 PM
    PCB DesignFrom schematic to autorouting what are your challenges in producing high-speed designs?591921669What the drill size to be use ...
By: Dhamodharann
30 Jul 2014 10:19 PM
    PCB SKILLUpload your SKILL files here. Give a brief summary of how to best use the SKILL code.10734416Re: Cmd prompt on HDL
By: eDave
28 Jul 2014 03:26 PM
    IC Packaging and SiP DesignPackaging solutions can make or break the cost budget. What design issues are you facing today? 105274Re: Unable to delete a cavity
By: aCraig
10 Jul 2014 09:41 AM
    High Level SynthesisModerator: Rajesh Radhakrishnan715IRUN script
By: tonio
23 Jul 2014 04:01 AM
    Mixed-Signal DesignThis Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andreas Lenz
95310Re: cadence running slow in ub ...
By: Andrew Beckett
30 Jul 2014 02:53 AM
    RAVEL DRC Programming for IC Packaging and PCBEverything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
511Re: Ravel IDE
By: ztzg
05 Mar 2014 05:48 AM
General Topics
Forum NameTopicsRepliesLast Post
    AnnouncementsNews, FAQs, and related info about how to best use the community.
Moderators: Community Operations
1620Re: Is there a Concept HDL for ...
By: Andrew Beckett
27 May 2014 12:07 AM
    Cadence Academic NetworkFOR ACADEMIC INSTITUTIONS: Share your approaches in design and the use of Cadence tools with fellow students and faculty.
Moderator: Patrick Haspel
126301Re: Learning ORCAD Capture, PS ...
By: steve
27 Jun 2014 04:37 AM
    Feedback, Suggestions, and QuestionsProvide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
211526Missing Polynomial Error
By: nicksantos13
28 Jul 2014 03:24 AM
    JobsPost jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.5357Great Opportunities in EDA, AR ...
By: epeefencer
11 Feb 2014 06:38 PM

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