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 e-Support in Synopsys' VCS ? 

Last post Thu, Nov 8 2007 4:58 PM by archive. 0 replies.
Started by archive 08 Nov 2007 04:58 PM. Topic has 0 replies and 850 views
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  • Thu, Nov 8 2007 4:58 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
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    e-Support in Synopsys' VCS ? Reply

    Truth, FUD or humor?

    Rumor has it that Synopsys are working on supporting e in VCS! For those of you who haven't seen the thread on the Verification Guild, here is a link.

    As an e user that can only be good news. Right? Or are we also going to see a VMM-for-e bomb, similar to the URM/VMM/AVM (and now OVM) SystemVerilog confusion? Will code be portable between simulators? How about eVCs?

    Say the rumor is true, I'd be very interested to see what the e user base has to say.

    Cheers,

    -Stelix.


    Originally posted in cdnusers.org by stelix
    • Post Points: 0
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Started by archive at 08 Nov 2007 04:58 PM. Topic has 0 replies.