Hi Vivek.Originally posted in cdnusers.org by stephenh
That's a very good question! Fortunately the URM (Universal Reuse Methodology) is designed specifically for this problem.
Whether you choose to code in e, SystemVerilog or SustemC, the methodology guides you through building a reusable testbench based on modular components. These guidelines have been developed through very close cooperation between Cadence and many customers over several years, so they really work.
The idea is to build everything in component form (e.g. bus interface components, sequence generators, protocol layering).
Each component is then used in a "testbench" that itself is designed to be plugged into a higher level testbench if needed.
You should take a look at http://myipcm.cadence.com/ for the online books that describe the methodology.
Also, get in touch with your local Cadence AE who can help you plan you verification.