Andy, you raise a variety of interesting issues!Originally posted in cdnusers.org by stelix
I will start by concentrating on one of your comments:
date, the reuse of verification plans from block to system level has
> more akin to a salvage operation. That is, elements of each of
> level plans have been physically included in the system level
> system level goals, weights and milestones.
Indeed this is very true. Cut-n-paste is a very common reuse practice ;-)
So when I reuse my DDRctrl vPlan to, say, the CoreA level vPlan, I may, or may not be interested in running the full plan. Why is that?
Well, my goals and weights could change depending on the application I am interested in. When I first design the DDRctrl, I really need to be very exhaustive. I may need to include a variety of metrics, like code coverage or formal model coverage. Now, when I instantiate my DDRctrl block several times and integrate it into my CoreA and CoreB designs, I want to select certain aspects of the vPlan, most likely the ones that pertain to interfacing with the core logic rather than the memory. I may not want to include formal model coverage anymore, since I am not running formal at the (sub)system level. I may want to combine such coverage with, say, software coverage. And so on.
In your opinion, who should be responsible for vPlan reuse in an engineering team? What are some good practices that a verification specialist, in charge of compiling a block-level vPlan, needs to apply to ensure reuse at the (sub)system level?