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 Verification with system verilog 

Last post Thu, Oct 18 2007 1:04 AM by archive. 2 replies.
Started by archive 18 Oct 2007 01:04 AM. Topic has 2 replies and 1020 views
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  • Thu, Oct 18 2007 1:04 AM

    • archive
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    Verification with system verilog Reply

    Verification environment implementation with system verilog.


    Originally posted in cdnusers.org by jagannadh.sv
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  • Thu, Oct 18 2007 1:09 AM

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    RE: Verification with system verilog Reply

    The question is : I am real satisfied user of IUS, now i am upgrading my self with system verilog, i have licensed version of IUS5.4, I started writing small programs and try running in IUS5.4 which i was using it for verilog before. when i started learning some programs which has classses, and try to compile, it is compiling fine but not not simulation showing that "This needs a seperate license", Does it really need a seperate license or any other solution?


    Originally posted in cdnusers.org by jagannadh.sv
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  • Fri, Oct 19 2007 7:59 AM

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    RE: Verification with system verilog Reply

    Hi jagannadh.sv

    Could you please post the log file and your test bench writing in system verilog?
    Cadence IUS low version can’t support the some features of system verilog.These
    features could find in the document of the tool installing directory.

    shawn lieu


    Originally posted in cdnusers.org by shawn-1
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Started by archive at 18 Oct 2007 01:04 AM. Topic has 2 replies.