We are actively working with Mentor on the technical details, but in response to your questions:
1) How much of the current URM will become part of OVM?
All of the current URM SystemVerilog Class-based methodology will become part of OVM, so existing URM users will be able to seamlessly transition to OVM. More importantly, any URM VIP that is developed will be interoperable with the rest of the world that adopts OVM.
2) Will OVM support the same set of foreign languane interfaces (e.g. will integrating an e TB module change/still work)?
Cadence and Mentor have both been providing multi-language verification tool & methodology support and we definitely plan to make sure that OVM will provide at least the same level of support as Mentor provides today with SystemC and Cadence provides with e and SystemC. This will enable users to reuse their SystemVerilog VIP to connect to both RTL and SystemC TLM models, and enable plug & play VIP between OVM SystemVerilog VIP and eRM VIP.
3) Will development of non SV modules (e.g. e) continue alongside OVM?
The short answer is yes. As you know, there is a lot more to verification beyond SystemVerilog testbenches. At Cadence we have developed the Incisive Plan to Closure Methodology (IPCM) which is a complete methodology spanning block to system level verification, from verification planning to coverage closure, and includes assertions, coverage-driven testbench reuse, and SystemC TLM, HW/SW co-verification, and Hardware-assisted system verification. URM has been a key component of IPCM for developing reusable SystemVerilog and e coverage-driven testbenches, and since OVM will be a superset of URM, we fully plan to make sure that OVM fits within IPCM. To your specific question about e, we continue to evolve the e Reuse Methodology, and we will make sure that eRM VIP will plug & play with SystemVerilog OVM VIP.
4) When is IUS 6.2 due?
6.2 is planned to be release in November.Originally posted in cdnusers.org by mstellfox