In the future, it would be better to start a new topic when asking a different question. This is also unrelated to SV and should go in the Simulation forum.
Now for the answer which I'm copying directly from the NC-Verilog Simulator Help docs.
Generate negative timing check (NTC) delays, but do not execute timing checks.
You can use the -notimingchecks option to turn off all timing checks in your design. However, if you have negative timing checks in the design, this option also disables the generation of delayed internal signals, and you may get wrong simulation results if the design requires these delayed signals to function correctly. That is, if you have negative timing checks, simulation results may be different with -notimingchecks and without -notimingchecks.
Use the -ntcnotchks option instead of the -notimingchecks option if you want the delayed signals to be generated but want to turn off timing checks. This option removes the timing checks from the simulation after the NTC delays have been generated.
If you are running the simulator in single-step mode with the ncverilog command, use the +ncntcnotchks option.Originally posted in cdnusers.org by tpylant