When verify a CPU, I encounter a SV functional coverage problem.
I'd like to check whether there are some back-to-back instructions sequence happened that I am interested in.
Like the instruction sequence:
Inst_1 R1, R2
Inst_4 R3, R4
Inst_9 R2, R2
But how to define the cover_group? AFAIK, there are control coverage and data coverage, shall I combine them together to get the Instruction sequence coverage?
Another questions that always confused me: I have a transaction generator and monitor(which connected input driver). Shall I get coverage from transaction generator directly or from the monitor connected input driver? IMHO, they are the same. But, what's your opinion?
Any suggestions are welcome!
Best regards,Originally posted in cdnusers.org by davyzhu