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 HD AUdio Interface 

Last post Tue, May 15 2007 3:31 AM by archive. 0 replies.
Started by archive 15 May 2007 03:31 AM. Topic has 0 replies and 868 views
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  • Tue, May 15 2007 3:31 AM

    • archive
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    • Joined on Fri, Jul 4 2008
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    HD AUdio Interface Reply

    Hi there
    I am starting System Verilog now and I am looking for the best practice for designing a System verilog interface for the HD Audio bus as define by Section 5 of ftp://download.intel.com/standards/hdaudio/pdf/HDAudio_03.pdf
    This bus requires a master controller generating the clock, the reset and the frame sync, which drives up to 16 codec (slaves) getting the clock, the reset and the sync. I am wondering about the best way of using interfaces capabilities as mod ports and parameters to define a suitable intercae.

    I am starting with this

    interface hda_if  ();
      logic rstn;
      logic [15:0] sdi;
      logic sdo;  // bussed serial data output(s)
      logic bclk; // link 24.00-MHz clock
      logic sync; // 48 khz frame sync and outbound tag signal

      modport master (output rstn, output sync, output bclk, output sdo, inout sdi);
      modport slave (input rstn, input sync, input bclk, input sdo, inout sdi[0]);

      task init ();
          rstn = 0;
          sdo = 0;
          @(posedge bclk);

    - is it OK to define just sdi[0] in the slave modport ( a slave codec exposes just one SDI, while the master controller handles up to 16 SDI)? What about the other, unused sdi's?

    - should I define the clock as an interface port - e.g.  interface hda_if (input blck); I see this is done in the SPI example of the System verilog traing, still I wonder how it works for master and slave flavours. The general question is how to handle clocks in interfaces for a master/slave bus: I probably don get the point of declaring interface ports .... SHould I use this stile and use modports

    - what do you recommend about clock generation? Since he master is in charge to genreate bclk I wonder if it is preferred to add a clockgen in the interface decalration or in the master controller module only? e.g.
      default clocking bck_cb @(posedge bclk);
        default input #1 output #3;
        input sdi;
        output sdi;
        output sdo;
        output sync;

    - The clockgen generates an istance right? So I suppose it is not receommended to include in the interface (I would inclued the interface declaration in a verilog file .vh included in a number of files using the i/f). do you recommend to put the interface in a compiled packege instead?

    Sorry for this long email: I am eager to start with the right pace the project also fro a SW engineering standpoin
    Any suggestion to fix/improve my approach is really welcome

    Originally posted in cdnusers.org by marco.stanzani
    • Post Points: 0
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Started by archive at 15 May 2007 03:31 AM. Topic has 0 replies.