Cadence is providing SystemVerilog enabled versions of the AHB (and other) eVCs.Originally posted in cdnusers.org by stephenh
As you may be aware, Cadence has enhanced the eVC technology into a language neutral one called UVC - Universal Verification Components. These can be written in e, SystemVerilog, or SystemC, even a mixture of languages! Have a look at the IPCM documentation to see how it works.
Talk to your local Cadence AE or sales guy about the SV enabled AHB UVC and they can help you.