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 Equivalent of AHB eVC in system verilog 

Last post Thu, May 10 2007 5:44 AM by archive. 2 replies.
Started by archive 10 May 2007 05:44 AM. Topic has 2 replies and 1191 views
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  • Thu, May 10 2007 5:44 AM

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    Equivalent of AHB eVC in system verilog Reply

    Hi,

    Is anybody aware of an AHB verification component in system verilog similar to the AHB eVC in specman?

    I am not sure if there is one in cadence's verification component list.

    Thanks in advance.

    Rgds


    Originally posted in cdnusers.org by danyuk7
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  • Thu, May 10 2007 8:26 AM

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    RE: Equivalent of AHB eVC in system verilog Reply

    Cadence is providing SystemVerilog enabled versions of the AHB (and other) eVCs.
    As you may be aware, Cadence has enhanced the eVC technology into a language neutral one called UVC - Universal Verification Components. These can be written in e, SystemVerilog, or SystemC, even a mixture of languages! Have a look at the IPCM documentation to see how it works.

    Talk to your local Cadence AE or sales guy about the SV enabled AHB UVC and they can help you.

    Regards,
    Steve.


    Originally posted in cdnusers.org by stephenh
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  • Fri, May 11 2007 1:35 AM

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    RE: Equivalent of AHB eVC in system verilog Reply

    Steve,

    Thanks for the information.

    I will talk with the local cadence AE.

    Rgds,
    Suresh


    Originally posted in cdnusers.org by danyuk7
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Started by archive at 10 May 2007 05:44 AM. Topic has 2 replies.