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 SC-SV-Verilog interface 

Last post Mon, Apr 23 2007 9:08 PM by archive. 0 replies.
Started by archive 23 Apr 2007 09:08 PM. Topic has 0 replies and 879 views
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  • Mon, Apr 23 2007 9:08 PM

    • archive
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    SC-SV-Verilog interface Reply

       How does the Cadence simulator NCSim handle the hierarchical interface between SystemC, SystemVerilog and Verilog2001. i.e. if the lower level modules are in different languages. e.g. worklib.entity:arch.

    Regards,
    -Deepak


    Originally posted in cdnusers.org by dvp
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Started by archive at 23 Apr 2007 09:08 PM. Topic has 0 replies.