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 vhdl & system verilog 

Last post Wed, Mar 21 2007 1:10 AM by archive. 0 replies.
Started by archive 21 Mar 2007 01:10 AM. Topic has 0 replies and 918 views
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  • Wed, Mar 21 2007 1:10 AM

    • archive
    • Top 75 Contributor
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    vhdl & system verilog Reply

       Hi All,

    I have a very basic qn - jus picking up system. verilog -> if the testbench is in system verilog
    and the top level is in vhdl - will both the modules be able to talk to each other?

    Many Thanks in advance,
    indeb


    Originally posted in cdnusers.org by indeb
    • Post Points: 0
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Started by archive at 21 Mar 2007 01:10 AM. Topic has 0 replies.