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 interface for bidirectional pins  

Last post Sat, Mar 17 2007 12:13 AM by archive. 1 replies.
Started by archive 17 Mar 2007 12:13 AM. Topic has 1 replies and 1032 views
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  • Sat, Mar 17 2007 12:13 AM

    • archive
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    interface for bidirectional pins Reply

    Hi

    I trying to interface a bidirectional pin in sysytemverilog. in my interface declaration i have declared it as wire and in clocking block as inout...in my top module i'm using a reg to get values and then using the following syntax

    assign my_if.biDir_pinname = reg_name;

    in simulation i'm observing X. i also have to do a weak pullup. please guide on how to model and successfully interface bidirectional pins. i'm using cadence IUS5.83

    ThanksĀ 


    Originally posted in cdnusers.org by chaitu2k
    • Post Points: 0
  • Sat, Mar 17 2007 2:53 PM

    • archive
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    • Joined on Fri, Jul 4 2008
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    RE: interface for bidirectional pins Reply

    Hello,

    You will have to treat the wire in the interface like you would treat any wire in Verilog. It can only have one driver at a time. I believe you will have to conditionally assign reg_name:

    assign my_if.biDir_pinname = (enable_me) ? reg_name : 'bz;

    Here is a mini example:

    interface mod_if;
    wire [7:0] bidir_bus;
    logic enable1;
    endinterface : mod_if

    module one (interface my_if);
    assign my_if.bidir_bus = (enable1) ? 8'h11 : 8'hz;
    endmodule : one

    module two (interface my_if);
    assign my_if.bidir_bus = (enable1) ? 8'hz : 8'h22;
    endmodule : two

    module top();
    mod_if my_if();
    one m1 (my_if);
    two m2 (my_if);

    initial begin
    my_if.enable1 = 1;
    repeat (4)
    #1 my_if.enable1 = ~my_if.enable1;
    end

    initial $monitor(my_if.enable1,, my_if.bidir_bus);
    endmodule : top

    Kathleen Meade


    Originally posted in cdnusers.org by kameade
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Started by archive at 17 Mar 2007 12:13 AM. Topic has 1 replies.