We won't be supporting globals in the near term. However, you can easily duplicate this behavior using packages, which is a better programming style anyway. Originally posted in cdnusers.org by tpylant
From IEEE1800 LRM 19.2, "SystemVerilog packages provide an additional mechanism for sharing parameters, data, type, task, function, sequence, and property declarations among multiple SystemVerilog modules, interfaces, and programs. Packages are explicitly named scopes appearing at the outermost level of the source text (at the same level as top-level modules and primitives). Types, variables, tasks, functions, sequences, and properties may be declared within a package. Such declarations may be referenced within modules, macromodules, interfaces, programs, and other packages by either import or fully resolved name. It is also possible to populate packages with parameters, variables, and nets. This may be useful for global items that are not conveniently passed down through the hierarchy."
rand bit a;
Then you can import the package wherever you need access to the package contents:
test_c item = new;
Or you can refer to the package items directly:
globals::test_c item = new;