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 sys. verilog code - need explanation 

Last post Tue, Mar 6 2007 7:44 AM by archive. 3 replies.
Started by archive 06 Mar 2007 07:44 AM. Topic has 3 replies and 1402 views
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  • Tue, Mar 6 2007 7:44 AM

    • archive
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    sys. verilog code - need explanation Reply

    HI, I am new to s.verilog - any help with the code below will be great!
    what does the code below actually mean? anyone explain plz?

    why is LOC_IDLE triggered?

    LOC :
            begin
              varc_sel[3:0] = { LOC_DRAIN ,
                                      LOC_GETDEL ,
                                      LOC_BUFDEL ,
                                      LOC_IDLE } ;
              case (varc_sel[3:0])
                4'b1000 ,
                4'b0100 ,
                4'b0010 ,
                4'b0001 ,
                4'b0000 :
                  begin
                   
                  end
                default :
                  begin
                     $write("ERROR:");
                     $display(" Invalid arc in, fsm:SM, state:LOC") ;
                     $display(" Instance: %m");
                     $display(" Time: %t", $time);


    Originally posted in cdnusers.org by indeb
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  • Tue, Mar 6 2007 10:13 AM

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    RE: sys. verilog code - need explanation Reply

    Somewhere I assume varc_sel is defined to be an enum like: typedef enum bit [1:0] {LOC_DRAIN, LOC_GETDEL, LOC_BUFDEL, LOC_IDLE} loc_t; loc_t [3:0] varc_sel; The way enums work is that you can refer to the labels by name, but underneath there are actual values for those labels. By default, it starts with 0 and counts up. You can change the default behavior by providing your own values in the definition. If you used the defaults, then LOC_IDLE would be equal to 3 which would never be selected in the case. However, you could use the following enum definition to make the assignment one-hot: typedef enum bit [1:0] {LOC_DRAIN=1, LOC_GETDEL=2, LOC_BUFDEL=4, LOC_IDLE=8} loc_t; Tim


    Originally posted in cdnusers.org by tpylant
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  • Tue, Mar 6 2007 5:16 PM

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    RE: sys. verilog code - need explanation Reply

    hi tim, thanks alot - but the invalid arc is asserted - is this coz enc_idle is 3 - and it goes into the default?

    how does case work? - seems like a basic qn - but i jus moved from process to design...

    thanks so much!


    Originally posted in cdnusers.org by indeb
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  • Tue, Mar 6 2007 7:23 PM

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    RE: sys. verilog code - need explanation Reply

    Yes, you are correct. The way the case works is it looks at the value of varc_selA and then selects the branch that matches the value. In the example, if the value is 8, 4, 2, 1, or 0 it will branch to the 'begin...end'. If it doesn't match any branch, then the default branch will be executed.

    I'm reposting my previous text since the formatting got screwed up.

    Somewhere I assume varc_sel is defined to be an enum like:

    typedef enum bit [2:0] {LOC_DRAIN, LOC_GETDEL, LOC_BUFDEL, LOC_IDLE} loc_t;
    loc_t varc_sel;

    The way enums work is that you can refer to the labels by name, but underneath there are actual values for those labels. By default, it starts with 0 and counts up. You can change the default behavior by providing your own values in the definition. If you used the defaults, then LOC_IDLE would be equal to 3 which would never be selected in the case. However, you could use the following enum definition to make the assignment one-hot:

    typedef enum bit [2:0] {LOC_DRAIN=1, LOC_GETDEL=2, LOC_BUFDEL=4, LOC_IDLE=8} loc_t;


    Originally posted in cdnusers.org by tpylant
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Started by archive at 06 Mar 2007 07:44 AM. Topic has 3 replies.