Posted By bryan on 2/26/2007 3:04 PM
I believe that signals declared within a generate are scoped to the generate. If true that would seem to say no to your question. Also our coding style is to declare all signals at the top of the file and then put all the code at the bottom. Inline declarations would not also us to conform to that practice.
I really looking for a LRM based answer so I can decide if this is a tool issue or just the way that generates are interpreted.
Clause 12.4 of the Verilog LRM 2005 states
"Generate schemes are evaluated during elaboration of the model. Elaboration occurs after parsing the HDL and before simulation; ..."
Statements within the generate block must therefore all be syntactically correct - the compiler should give an error if it encounters illegal code (such as use of undeclared signals), even if the generate block is subsequently skipped during elaboration.
Originally posted in cdnusers.org by dl_doulos