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 Waveform of task in class? 

Last post Sun, Feb 4 2007 10:37 PM by archive. 1 replies.
Started by archive 04 Feb 2007 10:37 PM. Topic has 1 replies and 1064 views
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  • Sun, Feb 4 2007 10:37 PM

    • archive
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    Waveform of task in class? Reply

    Hi all,

    We all know that tasks in module can be viewed in simvision by add a "probe -tasks".
    But how to see waveform of task in class?

    BTW, I use IUS583.

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
    • Post Points: 0
  • Fri, Feb 9 2007 10:00 AM

    • archive
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    RE: Waveform of task in class? Reply

    I saw the same/similar post in comp.lang.verilog, here is my reply to that post>>

    Ajeetha, CVC
    www.noveldv.com

    I don't use IUS, but going by other simulators, SV class dumping to
    waveform is not something as easy as that of modules, hence this may
    be not yet implemented feature. IMHO in many cases one can do without
    it. As we speak I'm writing a paper on Advanced Debugging for SV
    testbenches for SNUG India 2007. That talks about special approaches
    for testbenches. Some key points:

    1. It really helps if the environment is layered - be it VMM or AVM
    etc. I don't know much about uRM except its name, hope it has similar
    layered approach.
    2. If #1 is true, then the "task in waveform" is required only for
    "command transactor" or BFM layer. And there we do have a virtual
    interface, simply add few extra debug signals to that interface and
    update the class members to that interface. This approach is detailed
    in our 2006 SJ SNUG paper as well.

    3. Even for any class this approach #2 works as a workaround.
    4. For higher level models, breakpoints, transaction tracking etc. is
    important. We are looking at Verdi, command line debugger etc. for
    this.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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Started by archive at 04 Feb 2007 10:37 PM. Topic has 1 replies.