Posted By davyzhu on 1/15/2007 12:08 AM
Hi all, Is there any good methods to write SystemVerilog transaction sequence dependency constraint? For example, in below SV code, I want to always generate IDLE transaction after WRITE (i.e. WRITE after WRITE or READ after WRITE is illegal). //--- SV code start--- //define transactions typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t; class Packet; ... rand cmd_t cmd; ... endclass Packet p; initial repert(20) begin p = new(); p.randomize(); end //--- SV code end--- Best regards, Davy
Hi Davy,
Since you're looking just one step into the past, you could simply maintain a variable with the previous transaction type, use it in a constraint, and update its value after generating each new transaction. For example:
cmd_t prev_cmd = WRITE;
Packet p = new;
initial
repeat (20) begin
// apply constraint
assert( p.randomize() with {if (prev_cmd ==WRITE) cmd==IDLE } ) else $fatal;
// do something with p here
...
// update prev value for the next iteration
prev_cmd = p.cmd;
end
Now, if you want to generate more interesting sequences of transactions with a certain structure to them, you should create a new class - a sequence, which generates a stream of transactions based on some "control knobs" you set in the class instance. You can then have multiple (inherited) subtypes of that sequence class, each generating a different kind of sequence, with different knobs.
Regards,
Zeev.
Originally posted in cdnusers.org by zeevk