Posted By DM on 3/06/2007 5:12 PM
I'll be calling verilog tasks from SV classes. We'll be using VCS for simulations. Do u think this would support what u've suggested in the 1st step (reply to Mayank ).
or shud i go for the trigger method?
In the example you have shown, interface & class are SV Files or should the interface be some header/include file. And should the always block be running in the back ground all the time?
is my_trigger some kind of clock or ??
Which VCS version do you use? I'm sure the trigger way would work. Please give it a try yourself or send me an (ajeetha <> gmail) example code, I will fix and send it across.
BTW, what does VCS have to do with CDNUser forum :-) Your success rate is better if you post in verificationguild.com or www.svug.org
Originally posted in cdnusers.org by ajeetha