Home > Community > Forums > Functional Verification > Calling VHDL procedures in SystemVerilog Testbench.

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Calling VHDL procedures in SystemVerilog Testbench. 

Last post Sat, Dec 23 2006 7:56 AM by archive. 13 replies.
Started by archive 23 Dec 2006 07:56 AM. Topic has 13 replies and 3499 views
Page 1 of 1 (15 items)
Sort Posts:
  • Sat, Dec 23 2006 7:56 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    Calling VHDL procedures in SystemVerilog Testbench. Reply

    Is there a way to call VHDL procedures in a SV TB without translating them into SV tasks.. ?


    Originally posted in cdnusers.org by mirzani
    • Post Points: 0
  • Fri, Jan 5 2007 1:50 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Hi Mirzani.

    Hierarchical references to VHDL are not supported yet. I believe this is due to restrictions in the VHDL specification.
    I've been told this will change in the next version of VHDL, but I don't know any more than that.

    Steve.


    Originally posted in cdnusers.org by stephenh
    • Post Points: 0
  • Mon, Jan 29 2007 8:39 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    I should have used the word 'import' instead of call .
    I was wondering if there is an equivalent hdl_task(VERA) to import the VHDL procedures placed in a separate package..


    Originally posted in cdnusers.org by mirzani
    • Post Points: 0
  • Fri, Feb 9 2007 10:19 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Though not in LRM, in principle SV DPI can be extended for this. But why wait? I've been doing this for several years now with little WA. Pseudo-code:

    VHDL
    =======
    procedure vhdl_proc;...

    entity dummy (call_vhdl_proc : in bit)
    ...

    arch..
      process (call_vhdl_proc)
         vhdl_proc

    Verilog
    --------

    // Instantiate the dummy VHDL, toggle the "call_vhdl_proc"
       
    HTH
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
    • Post Points: 0
  • Mon, Mar 5 2007 6:28 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Hi,  I would also like to know if there is a way to map verilog tasks to system verilog tasks. Trying to build sys verilog wrappers around verilog tasks


    Originally posted in cdnusers.org by DM
    • Post Points: 0
  • Mon, Mar 5 2007 7:03 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Posted By DM on 3/05/2007 6:28 PM
    Hi,  I would also like to know if there is a way to map verilog tasks to system verilog tasks. Trying to build sys verilog wrappers around verilog tasks

    Hi DM,
          You don't really need any mapping - SV is on top of Verilog and is 100% backward compatible and hence this mapping is not necessary.

    What exactly are your trying to do? Reuse module based tasks inside class based env? That will be little tricky and require some coding effort. Give us more details, we can suggest.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
    • Post Points: 0
  • Mon, Mar 5 2007 7:12 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Hi, Thanks for the reply. We'll be having a verification environment which includes basic verilog tasks. The upper level sys verilog TB will have to make use of these tasks. So how can I refer to these verilog tasks from sys verilog. Does importing help? or shud we wrap the verilog tasks & use something similar to hdl_task as in Vera??


    Originally posted in cdnusers.org by DM
    • Post Points: 0
  • Mon, Mar 5 2007 11:53 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Yes Same problem I am facing. I need to call [b] Verilog tasks defined in a module <> hierarchy [/b], from my [b] classes in SystemVerilog [/b].
    How can it be made possible ??

    even defining them as extern task<> in SystemVerilog, it's giving compile time error, saying no module defined.

    Is there any way to call them through Interface definition etc..??

    Regards
    Mayank


    Originally posted in cdnusers.org by mayank
    • Post Points: 0
  • Mon, Mar 5 2007 11:54 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Yes Same problem I am facing. I need to call Verilog tasks defined in a module <> hierarchy , from my classes in SystemVerilog .
    How can it be made possible ??

    even defining them as extern task<> in SystemVerilog, it's giving compile time error, saying no module defined.

    Is there any way to call them through Interface definition etc..??

    Regards
    Mayank


    Originally posted in cdnusers.org by mayank
    • Post Points: 0
  • Tue, Mar 6 2007 10:38 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Mayank,
          To call a task from within a class, one can go via virtual interface:

      interface my_if;
         task my_task;
     //

      class my_c;
        virtual my_if my_if_0;

        task call_task();
           my_if_0.my_task;

    However I've seen tools not fully supporting this yet/premamture support. Till then you are better off with a WA like:

      interface my_if;
         task my_task; endtask


         always @my_trigger begin
             my_task;
         end

    Then trigger this "my_trigger" from within the class.

    This was skeleton code, if you have more problems, show us full code or send it to me via email (ajeetha <> gmail), I will see if I can help.

    HTH
    Ajeetha, CVC
    www.noveldv.com  


    Originally posted in cdnusers.org by ajeetha
    • Post Points: 0
  • Tue, Mar 6 2007 10:40 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Posted By DM on 3/05/2007 7:12 PM
    Hi, Thanks for the reply. We'll be having a verification environment which includes basic verilog tasks. The upper level sys verilog TB will have to make use of these tasks. So how can I refer to these verilog tasks from sys verilog. Does importing help? or shud we wrap the verilog tasks & use something similar to hdl_task as in Vera??

    DM,
      Depends on how your "upper level SV TB" is modeled, do you use class or module there? One way I showed in reply to Mayank's post.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
    • Post Points: 0
  • Tue, Mar 6 2007 5:12 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    HI Ajeetha,
      I'll be calling verilog tasks from SV classes. We'll be using VCS for simulations. Do u think this would support what u've suggested in the 1st step (reply to Mayank ).
     or shud i go for the trigger method?
    In the example you have shown, interface & class are SV Files or should the interface be some header/include file. And should the always block be running in the back ground all the time?
    is my_trigger some kind of clock or ??
    Thanks
    Deepa


    Originally posted in cdnusers.org by DM
    • Post Points: 0
  • Tue, Mar 6 2007 8:12 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    DM,

    I don't knew, whether you have tried this or no, but you can go down to the hierarchy, to the module, from which the task is to be called, and map it at the top.

    Like:

    **************** Code Snippet ***************

    `define DUT top.i_module1

    module top();

    // your TB description

    // To invoke the task in module1

    initial begin
    'DUT.task-name; // "task-name" is the name of the task defined in module-1
    ...
    end

    // module instantiation

    mod-name module1 ( //port mapping );

    ******************************************************************

    This should work.

    - Vivek


    Originally posted in cdnusers.org by prasad_vc
    • Post Points: 0
  • Wed, Mar 7 2007 1:42 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Posted By DM on 3/06/2007 5:12 PM
    HI Ajeetha,
      I'll be calling verilog tasks from SV classes. We'll be using VCS for simulations. Do u think this would support what u've suggested in the 1st step (reply to Mayank ).
     or shud i go for the trigger method?
    In the example you have shown, interface & class are SV Files or should the interface be some header/include file. And should the always block be running in the back ground all the time?
    is my_trigger some kind of clock or ??
    Thanks
    Deepa

    Deepa,
          Which VCS version do you use? I'm sure the trigger way would work. Please give it a try yourself or send me an (ajeetha <> gmail) example code, I will fix and send it across.

    BTW, what does VCS have to do with CDNUser forum :-) Your success rate is better if you post in verificationguild.com or www.svug.org


    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
    • Post Points: 0
  • Wed, Mar 7 2007 1:43 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Calling VHDL procedures in SystemVerilog Testbench. Reply

    Posted By prasad_vc on 3/06/2007 8:12 PM
    DM,

    I don't knew, whether you have tried this or no, but you can go down to the hierarchy, to the module, from which the task is to be called, and map it at the top.

    Like:

    **************** Code Snippet ***************

    `define DUT top.i_module1

    module top();

    // your TB description

    // To invoke the task in module1

    initial begin
    'DUT.task-name; // "task-name" is the name of the task defined in module-1
    ...
    end

    // module instantiation

    mod-name module1 ( //port mapping );

    ******************************************************************

    This should work.

    - Vivek
    Vivek,
        I would really doubt if it will work in class based environment, AFAIK the class-to-module communication is via virtual interface.

    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
    • Post Points: 0
Page 1 of 1 (15 items)
Sort Posts:
Started by archive at 23 Dec 2006 07:56 AM. Topic has 13 replies.