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 SystemVerilog Data-types (code) 

Last post Wed, Sep 20 2006 2:12 AM by archive. 2 replies.
Started by archive 20 Sep 2006 02:12 AM. Topic has 2 replies and 6163 views
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  • Wed, Sep 20 2006 2:12 AM

    • archive
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    SystemVerilog Data-types (code) Reply

    Hi,
    I am sharing the little work i did on SystemVerilog. This can be the starting point for anyone new to the language. If you all can enhance this by adding your part, will really make an practical guide for the language.

    // Program for Data-Types of SystemVerilog
    // Author : Vivek Prasad
    // Date   : 15 Sep 2006
    // Covers : shortint, int, real, time, reg, bit, logic, string, enum, struct
    //          class, functions, tasks.

    module data_types;

    //**************************Data-Types**************************************//
      time dt_time         = 1ms;    // dt_time is defined as time variable.
      shortint dt_decimal  = 10;     // 16-bit representation of decimal 10.
      shortint dt_octal    = 8'o17;  // Octal "317" assigned to dt_octal.
      bit [7:0]dt_binary   = 8'd42;  // dt_binary will be "00101010".
      logic [7:0]dt_hex    = 8'hAX;  // 16-base-AB
      byte     dt_byte     = "V";    // ASCII "V" character.
      int      dt_signed   = -5;     // 32-bit represen'n of -5 in one's compl.
      real     dt_real     = 3.141;  // Real number representation.
      real     dt_exp      = 1.0e6;  // Floating point representation.
      reg [3:0]dt_reg      = 4'b01XZ;// 4-value "reg" data-type.
    //  string   dt_name     = "{Vivek Prasad\n}";  // Not supported by ncsim5.6
    //  int dt_cast;   // could not obtain the reult.
    //************************Data-Types****************************************//

    //****************************Enum********************************************//
      typedef enum bit {NO,YES} boolean;
      boolean  dt_enum;      // To use boolean as variable-type, use typedef.

      assign dt_enum = YES;
    //****************************Enum********************************************//

    //****************************Struct******************************************//
      typedef struct packed {
                     bit [7:0] opcode;
                     bit [23:0]addr;
                     } IR;   // To use IR as variable-type, use typedef.
      IR dt_instr;
    //****************************Struct******************************************//
     
    //****************************Class*******************************************//
      class adder;
        int a;
        int b;
        int sum;
       
        task add();
          sum = a + b;
        endtask

        function void init();
          a = 2;
          b = 5;
          $display("a=%d & b=%d",a,b);
        endfunction
      endclass

      adder dt_add = new();
    //****************************Class*******************************************//
         
    //****************************Casting*****************************************//
    //  dt_cast = int'(3.141);
    //****************************Casting*****************************************//

    //****************************Initialization**********************************//
      initial
      begin
        $display("Time Literal : %t\n",dt_time);
        $display("Decimal Literal : %d\n",dt_decimal);
        $display("Octal Literal : %o\n",dt_octal);
        $display("Binary Literal : %b\n",dt_binary);
        $display("Hex Literal : %h\n",dt_hex);
        $display("Byte Literal : %h\n",dt_byte);
        $display("Signed Literal : %d\n",dt_signed);
        $display("Real Literal : %f\n",dt_real);
        $display("Float Literal : %f\n",dt_exp);
        $display("Reg Literal : %b\n",dt_reg);
    //    $display("String Literal : %s\n",dt_string);
        $display("Enum Data-type : %b\n",dt_enum);
        $display("Structure Example");
        dt_instr.opcode = 8'h12;
        dt_instr.addr   = 24'habcdef;
        $display("Struct Member1 : %h",dt_instr.opcode);
        $display("Struct Member2 : %h\n",dt_instr.addr);
        $display("Class Example");
        dt_add.init();
        dt_add.add();
        $display("Sum = %d\n",dt_add.sum);
    //    $display("Casting = %d\n",dt_cast);
        $finish;
      end
    //****************************Initialization**********************************//
    endmodule

    // Output, as on ncsim5.6

    // Time Literal    :  1000000 
    // Decimal Literal :  10
    // Octal Literal   :  000017
    // Binary Literal  :  00101010
    // Hex Literal     :  ax
    // Byte Literal    :  56      // ASCII Value of "V"
    // Signed Literal  :  -5
    // Real Literal    :  3.141000
    // Float Literal   :  1000000.000000
    // Reg Literal     :  01XZ
    // Enum Data_type  :  0
    // Structure Example
    // Struct Member1  :  12
    // Struct Member2  :  abcdef
    // Class Example
    // a = 2 & b = 5
    // Sum = 7


    Vivek Prasad


    Originally posted in cdnusers.org by prasad_vc
    • Post Points: 0
  • Wed, Sep 20 2006 9:45 AM

    • archive
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    • Joined on Fri, Jul 4 2008
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    RE: SystemVerilog Data-types (code) Reply

    This is a great showing of all the different data types in SV. In actual usage, I would recommend putting the typedefs into packages. This cleans up your code and makes it easy to reuse the data types since they are in a stand alone package/file.

    Example:

    [u]types_pkg.sv[/u]
    package types_pkg;
    typedef enum bit {NO,YES} boolean_t; // adding _t extension makes it easier to identifiy as a typedef
    typedef struct packed {
    bit ?:0] opcode;
    bit ?:0]addr;
    } IR_s; // To use IR as variable-type, use typedef.
    ...
    endpackage : types_pkg

    Then you "import" the package(s) into whatever modules you need those typedefs.

    Example:

    module data_types;
    import types_pkg::*;
    ...
    boolean_t flag; // boolean is a typedef from types_pkg
    ...
    endmodule

    You could also put the display statements into a general purpose task and put that task into the package as well.

    Thanks for the examples,
    Tim


    Originally posted in cdnusers.org by tpylant
    • Post Points: 0
  • Tue, Jan 23 2007 3:21 PM

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    RE: SystemVerilog Data-types (code) Reply

    Just to complete this examples for strings (partially works in IUS5.83 and complete in IUS6.0)

    ----file: top.v-----------
    module top ();
    /import "DPI-C" context pass_string_c= task pass_string_sv(input string a);

    import "DPI-C" context string_c2v_c= function string string_c2v_sv();

    string some_string;

    // This doesnt work in IUS583, will work in IUS6.0
    export "DPI-C" print_string_c = function print_string_sv;

    function void print_string_sv(input string aaa);
    $display("Print_string from Verilog % s", aaa);
    endfunction

    initial
    begin
    some_string = "pass it ON";
    // comment in line below when running IUS6.0
    pass_string_sv(some_string); // pass string to C
    $display("Verilog: % s \ n", string_c2v_sv() ); // get string from C
    $finish;
    end

    endmodule

    ----file: main_task.c----------
    #include
    #include

    // to use io_printf
    #include

    void pass_string_c(const char* a) {
    printf("C: %s \n", a);
    print_string_c("string passed from C"); // This doesnt work in IUS583
    }

    const char* string_c2v_c(void) {
    io_printf("C: give up a string \n"); // io_printf from vpi will print to ncsim.log file, can use printf()
    return "Gimme String";
    }

    -------File: RUN_NC (script)-------------
    rm -r INCA_libs
    rm *.so
    rm *.log
    rm *.h

    # Create .h file for Exported tasks/functions only
    # (imported function do NOT need .h file):
    ncverilog +sv top.v +ncdpiheader+dpi.h +elaborate +ncelabargs+-messages

    # ncvlog -sv top.v -mess
    # ncelab top -sv -dpiheader dpi.h -mess

    gcc -fPIC -shared -o main_task.so main_task.c -I/`ncroot`/tools/inca/include

    ncverilog +sv top.v +sv_lib=main_task.so +access+r +ncsimargs+"-sv_root ./"

    -----simulation results-----
    ncsim> run
    C: pass it ON
    Print_string from Verilog string passed from C
    Verilog: C: give up a string
    Gimme String

    Simulation complete via $finish(1) at time 0 FS + 0


    Originally posted in cdnusers.org by tmackett
    • Post Points: 0
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Started by archive at 20 Sep 2006 02:12 AM. Topic has 2 replies.