Hi Marco,Originally posted in cdnusers.org by email@example.com
Cadence has also been developing a SystemVerilog testbench methodology, called the "Universal Reuse Methodology" (uRM), as part of the complete Incisive Plan to Closure Methodology development effort. The methodology includes documentation, and code examples. If you can send me an email (firstname.lastname@example.org), I can put you in touch with an AE who can show you how to leverage the uRM methodology. This should make it much easier for you to come up to speed on how to use SystemVerilog for building testbenches. It also includes examples on how to connect SystemVerilog verfication components to e verification components.