Hi,Originally posted in cdnusers.org by bijitm
I am trying to verify a VHDL-verilog mixed design with IFV 5.83-s003. When I am trying to compile all the modules and entities, I am getting several error messages of the following kind,
halcheck *E, STDPKG (filename): The IEEE package 'std_logic_arith' should not be used.
halcheck: *E, RTLNOP (filename): Primitive instances are not expected in an RTL design.
mu1udp #0 MUX2_UDP0 (Y,S,A,B);
I have identified that there is one verilog file which when added to the .f file creates this problem. Otherwise, formalbuild goes through well. However, as soon as I add this file, errors are flooded regarding the other VHDL files in the design. I cannot change the design and rectify these problems. I have to verify the design the way it is. What is the solution to this? Is there any way to disable HAL checks or change the severity from 'Error' to 'Warning' so that the formalbuild goes through?
Thanks in anticipation.