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 verifying clock divider 

Last post Wed, Apr 25 2007 12:04 PM by archive. 2 replies.
Started by archive 25 Apr 2007 12:04 PM. Topic has 2 replies and 1397 views
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  • Wed, Apr 25 2007 12:04 PM

    • archive
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    verifying clock divider Reply

    Hello,

    How do you verify your clock divider logic, generally? Would you recommend assertions to verify clock dividers? Would this be a good candidate for formal verification?

    Any info will be appreciated.


    Regards,
    Amir


    Originally posted in cdnusers.org by Sibil
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  • Wed, Apr 25 2007 7:41 PM

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    RE: verifying clock divider Reply

    Hi Amir:

    I have used IFV with a clock divider logic before. It works out quite well for me. I remember what we have done with that module was to check based on certain control signals, output clock should be divided down accordingly. The assertions are like given the control, for how many rising edge of the input clock, you are expecting a rising edge of the divided down clock. For us, all assertions got proven within minutes. However in general, the performance depends on how big your divider logic is.

    Regards,

    Bin


    Originally posted in cdnusers.org by binju
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  • Fri, Jul 6 2007 8:05 AM

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    RE: verifying clock divider Reply

    Hi,

    I have written a simple formal verification IP for clock divider. I'm attaching it to this email. It might help somebody.

    Regards,
    Amir


    Originally posted in cdnusers.org by Sibil
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Started by archive at 25 Apr 2007 12:04 PM. Topic has 2 replies.