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 Can I force or probe a signal in vhdl module from verilog top testbench? 

Last post Thu, Feb 8 2007 12:07 AM by archive. 6 replies.
Started by archive 08 Feb 2007 12:07 AM. Topic has 6 replies and 3906 views
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  • Thu, Feb 8 2007 12:07 AM

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    Can I force or probe a signal in vhdl module from verilog top testbench? Reply

    At 2/07/2007 10:01 AM a message was posted to a thread you were tracking. -- RE: Using the Forum by hubertx

    Can I force or probe a signal in vhdl module from verilog top testbench?
    I heard some simulator has its own way to do that easily, can you give me a example code to do that with ncsim?


    Originally posted in cdnusers.org by foster
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  • Thu, Feb 8 2007 12:17 AM

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    RE: Can I force or probe a signal in vhdl module from verilog top testbench? Reply

    Hi Hubert,

    from a VHDL module you can probe/force any VHDL or Verilog signal using ncmirror and ncforce, refer to the following documentation:

    http://sourcelink.cadence.com/docs/files/Release_Info/Docs/ncvhdl/ncvhdl5.83/applications.html#1044121

    There is no mechanic to access a VHDL object from a Verilog module today.

    As a workaround you may instantiate a VHDL Mirror component inside your Verilog module. Inside this VHDL component you can use the ncmirror and ncforce functions as described above and connect the probed/force signals through the ports to local Verilog signals.

    F.


    Originally posted in cdnusers.org by foster
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  • Thu, Feb 8 2007 4:31 AM

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    RE: Can I force or probe a signal in vhdl module from verilog top testbench? Reply

    Actually you can access a VHDL object from a Verilog testbench using the $nc_force or $nc_mirror routines. They're relatively new to NC-Verilog. I just looked them up and I see that they're documented in Chapter 19 of the NC-Verilog Simulator Help manual.


    Originally posted in cdnusers.org by TAM
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  • Fri, Feb 9 2007 10:52 AM

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    RE: Can I force or probe a signal in vhdl module from verilog top testbench? Reply

    Thank you very much, I'll try that.


    Originally posted in cdnusers.org by hubertx
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  • Mon, May 7 2007 12:34 AM

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    RE: Can I force or probe a signal in vhdl module from verilog top testbench? Reply

    Hi,
    we are facing a similar isue. We need to check connectivity between a source signal which is instantiated in a VHDL module and a destination signal which is instantiated in a Verilog noe. It is not clear if and how to use $nc_force command, which requires a value ('0|1)) iwith Formal Verification tool. Does soembody have ever tried that?


    Originally posted in cdnusers.org by maurizios
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  • Mon, May 7 2007 9:08 AM

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    RE: Can I force or probe a signal in vhdl module from verilog top testbench? Reply

    In response to forcing signals in Formal, this cannot be done. To check connectivity, you would write a property to ensure the two signals are always the same like:

    // psl verify_signals : assert always (siga == sigb);

    If the source of the signal is a port of a module you can blackbox the module driving the signal or just use [b]cutpoint[/b] to free the driven signal from being driven by the design. Now IFV will drive this signal as a free input signal and allow you to verify the connectivity to the destination. Does this explaination make sense to you?


    Originally posted in cdnusers.org by jb
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  • Tue, May 8 2007 9:04 AM

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    RE: Can I force or probe a signal in vhdl module from verilog top testbench? Reply

    Related to the last couple of posts, there was a paper presented at CDNLive in SJ last year regarding connectivity checking.
     
    Session 1.8: Formal Analysis of Padring Mux-Logic Using IFV (Incisive Formal Verifier)

    It talks about using Formal Analysis and assertions as a much more efficient way to solve the connectivity problem.  You might find it useful. It can be found at:

    http://www.cdnusers.org/CDNLive/SiliconValley2006Proceedings/tabid/366/Default.aspx?topic=Functional%20verification


    Originally posted in cdnusers.org by ccc
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Started by archive at 08 Feb 2007 12:07 AM. Topic has 6 replies.