Hi Hubert,Originally posted in cdnusers.org by foster
from a VHDL module you can probe/force any VHDL or Verilog signal using ncmirror and ncforce, refer to the following documentation:
There is no mechanic to access a VHDL object from a Verilog module today.
As a workaround you may instantiate a VHDL Mirror component inside your Verilog module. Inside this VHDL component you can use the ncmirror and ncforce functions as described above and connect the probed/force signals through the ports to local Verilog signals.