Last year I attended CDNLive and really got a lot out of
it. The papers presented in the functional verification track gave great
perspectives on how customers were using Cadence tools to help verify their
designs. Although the designs were much different than what my company
designs, I was able to learn from the presenters and apply some things they
presented to what we are designing.
In addition to the paper presentations, the speakers were also excellent.
They shared their perspectives on problems facing designs today, how some of
these problems will be solved, and where the semiconductor industry was headed
in the future.
Not only was the content interesting, but the conference itself was well
run. The amount of time given to the presenters seemed to be the right
length, the number of breaks was appropriate, and there were always plenty of refreshments
I am going again this year and would definitely recommend it to others. Take a look at the conference website if you
Also, one particular presentation that may be of interest to this forum is on
Wednesday titled “Formal Analysis of Padring Mux-Logic Using IFV (Incisive
The abstract talks about automatically extracting assertions
from a specification for use with Formal Analysis to exhaustively verify and
achieve 100% coverage while reducing effort 4-10x. These are very lofty goals and it will be
interesting to hear how they did it.
Originally posted in cdnusers.org by weberrm