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 Which Assertion Language to Use? 

Last post Mon, Mar 6 2006 8:46 AM by archive. 0 replies.
Started by archive 06 Mar 2006 08:46 AM. Topic has 0 replies and 1055 views
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  • Mon, Mar 6 2006 8:46 AM

    • archive
    • Top 75 Contributor
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    Which Assertion Language to Use? Reply

            There are two standard assertion langages PSL (Property Specification Language) and SVA (SystemVerilog Assertions). They are both IEEE standards and they are both supported by most EDA vendors.

    Which one should I use?

    SVA is part of the SystemVerilog language so if your design is in SystemVerilog, SVA is a good choice.

    PSL is a property language designed to work with Verilog, VHDL, SystemVerilog and SystemC so if your design is VHDL or a mix of languages, PSL is a good choice.

    Both language offer similar capabilities but there are a couple of differences:

    • SVA assertions always have a clock. In PSL you don't have to evaluate an assertion on a clock edge.
    • PSL assertions are entered as comments in the code or in a separate file whereas SVA assertions are part of the RTL language.
    Regards,

        Anders Nordstrom
        Architect
        Incisive Formal
        Cadence Design Systems.


    Originally posted in cdnusers.org by andersn
    • Post Points: 0
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Started by archive at 06 Mar 2006 08:46 AM. Topic has 0 replies.