Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 NCSIM Internal Error 

Last post Wed, Jan 30 2008 8:06 AM by archive. 4 replies.
Started by archive 30 Jan 2008 08:06 AM. Topic has 4 replies and 5738 views
Page 1 of 1 (5 items)
Sort Posts:
  • Wed, Jan 30 2008 8:06 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    NCSIM Internal Error Reply

    Hi,

    I am in the process of running a multiple chip simulation for one of our FPGA based projects using the NCLAUNCH tool. I encountered a Fatal Error after running the simulation for around 8ms, the details of which are posted below :

    ncsim: *internal* (System virtual memory limit exceeded (0x5000/0xbfef9198)).
    Observed simulation time : 8991853460 PS + 3
    Please contact Cadence Design Systems about this problem
            and provide enough information to help us reproduce it.

    The complete run-time of the simulation is around 100ms. Please note, i did not dump any waveforms during the simulation run. Could you kindly update me more on this error and any solutions to deal with this?

    Thanks,
    Dina


    Originally posted in cdnusers.org by caddina
    • Post Points: 0
  • Wed, Jan 30 2008 12:32 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: NCSIM Internal Error Reply

    Hi Dina,

    There are a number of things that can cause a Virtual Memory limit issue.
    Can you provide a bit more information? Are you on Linux? 64bit or 32bit?
    What version of NC are you using? One thing you could do to help us sort this out would be to run your design with the -profile switch and send us the prof.out file that gets produced.
    It may take a bit longer to run but it could give us a hint. The fact that you are running out
    to a certain point in sim time and then running out of memory may point to some design construct. The prof.out will tell us.

    Best Regards
    Doug


    Originally posted in cdnusers.org by douge
    • Post Points: 0
  • Wed, Jan 30 2008 12:41 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: NCSIM Internal Error Reply

    Dina,

    Here are some other things you could do/check. If it applies to your particular simulation run.

    * Upgrade your software.

    Each successive NC-Verilog simulator release has shown significant improvement
    in memory efficiency. Thus, upgrading to the latest NC-Verilog simulator release
    always improves memory performance.

    * Limit access to those portions of a design being actively debugged.

    You can use an access control file to limit the scope of read, write, and
    connectivity access in a design. See the section, “Using -afile to Include an
    Access File,” in the chapter, “Elaborating with ncelab,” in the NC-Verilog
    Simulator Help for details on using an access control file.

    Similarly, you can further improve simulation speed and reduce memory usage by
    eliminating the need for line-based debug access to source code, for example,
    by eliminating line-based breakpoints. By default, the simulator does not
    retain this type of access. You can retain this type of access by using the
    ncvlog -linedebug option, but this option has a significantly negative impact on
    simulation performance.

    * Do not place probes on signals you do not need to debug.

    Placing probes on every signal in a design can consume more memory than the
    simulation model itself. Restricting the range of probe points to those portions
    of the design being actively debugged can save significant memory resources.

    * Run a simulation with timing checks disabled.

    Running a simulation without timing checks can save meaningful amounts of
    memory. The memory efficiency of these checks has been significantly improved in
    recent releases of the software, but they still add overhead to the simulation. You
    can disable timing checks from the command line, or you can enable and disable
    them for particular portions of the circuit using a timing control file. See the
    section, “Disabling Timing in Selected Portions of a Design,” in the chapter,
    “Elaborating with ncelab,” in the NC-Verilog Simulator Help, for more detailed
    information on timing control files.

    * Avoid overusing bidirectional transistor primitives in your design.

    The bidirectional transistor primitives are tran, tranif0, tranif1, and their
    resistive counterparts, rtran, rtranif0, and rtranif1. Overusing these primitives
    can significantly increase memory usage, so they should appear only in models in
    which true bidirectional behavior is desired. A single bidirectional primitive
    does not make much difference in memory usage, but the thousands or tens
    of thousands that can appear in a gate-level model can add up to significant
    simulation overhead. Therefore, when each pin of a bidirectional primitive has
    only a source or only a load, use a unidirectional primitive instead.



    Originally posted in cdnusers.org by douge
    • Post Points: 0
  • Thu, Jan 31 2008 3:55 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: NCSIM Internal Error Reply

    Hi Douge,

    Thanks for your inputs. It was really helpful. The Problem is now solved. I upgraded my exisitng nclaunch v5.5 software to a higher v5.8 version. The Internal NCSIM error vanished and the simulation ran successfully.

    Thanks!
    Cheers,
    Dina 


    Originally posted in cdnusers.org by caddina
    • Post Points: 0
  • Thu, Jan 31 2008 6:03 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: NCSIM Internal Error Reply

    Hi Dina,

    Glad your Internal error vanished. Have fun

    Best Regards
    Doug


    Originally posted in cdnusers.org by douge
    • Post Points: 0
Page 1 of 1 (5 items)
Sort Posts:
Started by archive at 30 Jan 2008 08:06 AM. Topic has 4 replies.