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 how to simulate ADC INL DNL with Cadence. 

Last post Thu, Jul 19 2007 9:04 AM by archive. 1 replies.
Started by archive 19 Jul 2007 09:04 AM. Topic has 1 replies and 3203 views
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  • Thu, Jul 19 2007 9:04 AM

    • archive
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    how to simulate ADC INL DNL with Cadence. Reply

      Hi everybody,
    I have designed an analog 10 bits DAC in CMOS 018u techno with cadence. I want to simulate the schematics to  obtain  the INL and DNL. can  Someone  help me about that  or give me a link where a Icould find more information ?? Is it possible with cadence or do i need to use another tool?

    Thanks for Ur help...


    Originally posted in cdnusers.org by isazul
    • Post Points: 0
  • Thu, Jul 19 2007 9:09 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
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    RE: how to simulate ADC INL DNL with Cadence. Reply

    there is a little mistake in the title as U see it`s not INL and DNL for an ADC but for a DAC

    thks


    Originally posted in cdnusers.org by isazul
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Started by archive at 19 Jul 2007 09:04 AM. Topic has 1 replies.