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  Post-Route Simulation does not give output for the first clock cycle Options 

Last post Thu, Apr 19 2007 7:49 AM by archive. 0 replies.
Started by archive 19 Apr 2007 07:49 AM. Topic has 0 replies and 1359 views
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  • Thu, Apr 19 2007 7:49 AM

    • archive
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    Post-Route Simulation does not give output for the first clock cycle Options Reply

    Hi,

    I designed a 3 stage pipelined floating point adder/subtractor (IEEE
    754 floating point arithmetic).


    I am using Xilinx ISE 9.1a environment to code and Modelsim to
    simulate.


    I am getting correct outputs for all the clock cycles in behavioral
    simulation. However, in Post-Route simulation, I am not getting
    output for the first data pair given for the arithmetic. In the next
    clock cycles, output is coming correctly. When I increased the period
    to 200 ns, output is coming correctly in the first clock cycle also.
    But, I did not understand why it is giving correct output when the
    period is increased to 200 ns from 80 ns.


    In the detailed Design summary produced after the Post-Route
    simulation, I saw that the minimum time period is 24 ns. But, I am
    getting output for the first clock cycle only when the period is
    increased to 200 ns. Please throw some light about what is happening.


    Thanks and Regards,


    Originally posted in cdnusers.org by techlife3
    • Post Points: 0
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Started by archive at 19 Apr 2007 07:49 AM. Topic has 0 replies.