Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Memory utilization 

Last post Wed, Apr 18 2007 9:02 AM by archive. 1 replies.
Started by archive 18 Apr 2007 09:02 AM. Topic has 1 replies and 1442 views
Page 1 of 1 (2 items)
Sort Posts:
  • Wed, Apr 18 2007 9:02 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    Memory utilization Reply

    Hi All,
    I am trying to understand why IUS 5.83 utilizes more physical memory for REG datatype than BIT datatype. For example
    `define    MAX_MEM    1048576*4
    module    sv_test;
    reg    [127:0]    memory[0:`MAX_MEM-1];        // unpacked
    integer    i;
    initial
    begin
        for (i=0; i<`MAX_MEM; i++)
         begin
          memory[i] = 0;
             end
         $display ("array data %d", memory[349]);
         $display ("array index %d", i);
    end
    endmodule

    In this example, the array uses twice as much RAM since it is of type REG. Can some one please explain why this is so?

    Thank you


    Originally posted in cdnusers.org by sreeramr
    • Post Points: 0
  • Wed, Apr 18 2007 9:11 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Memory utilization Reply

    In SystemVerilog, BIT is defined as a two-state variable, while REG is defined as a four-state variable. Since REG has twice as many states, it needs twice as much physical memory.

    Hope this helps!

    Dave Allen


    Originally posted in cdnusers.org by davea
    • Post Points: 0
Page 1 of 1 (2 items)
Sort Posts:
Started by archive at 18 Apr 2007 09:02 AM. Topic has 1 replies.