SystemVerilog is supported with Palladium.Originally posted in cdnusers.org by GaryHall
For In Circuit Emulation (ICE) and Synthesizable TestBench (STB) all HDL goes into the emulator. In this case only synthesizable design constructs are supported.
For Simulation Acceleration (SA), most of the testbench runs in IUS, the rest of the testbench and DUT run in Palladium. In this case the testbench constructs are handled by IUS and design constructs by Palladium.
We are constantly enhancing our SystemVerilog IEEE 1800 standard support with each new release containing more features than the previous one. Please get in contact with a local AE to discuss your exact requirements.
SVA will be supported in IXE5.0.