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 Is System Verilog is supported in Palladium? 

Last post Thu, Oct 12 2006 12:05 PM by archive. 1 replies.
Started by archive 12 Oct 2006 12:05 PM. Topic has 1 replies and 1736 views
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  • Thu, Oct 12 2006 12:05 PM

    • archive
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    Is System Verilog is supported in Palladium? Reply

    If yes, what exactly is supported?  How about SVA?


    Originally posted in cdnusers.org by minhnn
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  • Fri, Oct 13 2006 2:08 AM

    • archive
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    RE: Is System Verilog is supported in Palladium? Reply

    SystemVerilog is supported with Palladium.

    For In Circuit Emulation (ICE) and Synthesizable TestBench (STB) all HDL goes into the emulator. In this case only synthesizable design constructs are supported.

    For Simulation Acceleration (SA), most of the testbench runs in IUS, the rest of the testbench and DUT run in Palladium. In this case the testbench constructs are handled by IUS and design constructs by Palladium.

    We are constantly enhancing our SystemVerilog IEEE 1800 standard support with each new release containing more features than the previous one. Please get in contact with a local AE to discuss your exact requirements.

    SVA will be supported in IXE5.0.


    Originally posted in cdnusers.org by GaryHall
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Started by archive at 12 Oct 2006 12:05 PM. Topic has 1 replies.