I am new to design entry hdl.I do the exercise following the tutorial (concepthdl_tut.pdf)step by step. Originally posted in cdnusers.org by freeqwg
when finish the schematic[creating a schematic:basic],I got the following warning:
"INFO : HDL Power Symbol doesn't have voltage property. To turn off this warning please goto Tools->Options->Check and uncheck 'Voltage on HDL Symbols' option."
when i disable the "Voltage on HDL sysmbols", i can't get the verilog.v output.It tell me that "Msg Error(send EditFile request):Unable to launch editor".
Please help me,thanks.