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 Concept HDL Bus connection 

Last post Wed, Feb 6 2008 2:56 AM by archive. 1 replies.
Started by archive 06 Feb 2008 02:56 AM. Topic has 1 replies and 1074 views
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  • Wed, Feb 6 2008 2:56 AM

    • archive
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    Concept HDL Bus connection Reply

    In my design i am having Bus PPC_A<10..31>.it is splitted as PPC_A<17..31> to NVRAM and PPC_A<10..24> to Flash device.From this  memory block i want to take only one signal into top level called PPC_A<10..31>.So how to combine those signal into PPC_A<10..31> signal.

    Please help me.

    Thanks in Advance.


    Originally posted in cdnusers.org by lingam
    • Post Points: 0
  • Wed, Apr 9 2008 5:03 AM

    • archive
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    RE: Concept HDL Bus connection Reply

    Hello,
    The tool should do this automatically for you. However, to make my schematic easier to read, I always stick to the following conventions:

    When I draw a bus, I always show the entire scope of the bus. So in your case, if the bus is PPC_A<10..31>, and I only need <10..24> then I would always draw <10..31>, and then only create taps for <10>, <11>.... <24>.

    When jumping heirarchy levels, the same rule applies. Show the entire scope. Doens't matter if the upper level onyl requires 1 bit, I still connect them all. The resultant netlist is the same.

    Finally, I never use vectored pins on components. Hierarchical blocks are fine (you can change the number of bits to suit your need). Personally I find that it aids debug to show discrete pins on components. You will also avoid the pain of getting your design back to find that bit 0 is connected to 31, 1 to 30 etc.
    Hope that helped.


    Originally posted in cdnusers.org by vealmic@uk.ibm.com
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Started by archive at 06 Feb 2008 02:56 AM. Topic has 1 replies.