Hello,Originally posted in cdnusers.org by email@example.com
The tool should do this automatically for you. However, to make my schematic easier to read, I always stick to the following conventions:
When I draw a bus, I always show the entire scope of the bus. So in your case, if the bus is PPC_A<10..31>, and I only need <10..24> then I would always draw <10..31>, and then only create taps for <10>, <11>.... <24>.
When jumping heirarchy levels, the same rule applies. Show the entire scope. Doens't matter if the upper level onyl requires 1 bit, I still connect them all. The resultant netlist is the same.
Finally, I never use vectored pins on components. Hierarchical blocks are fine (you can change the number of bits to suit your need). Personally I find that it aids debug to show discrete pins on components. You will also avoid the pain of getting your design back to find that bit 0 is connected to 31, 1 to 30 etc.
Hope that helped.