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 Etch Width Assignment 

Last post Tue, Jan 29 2008 7:03 AM by archive. 3 replies.
Started by archive 29 Jan 2008 07:03 AM. Topic has 3 replies and 1619 views
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  • Tue, Jan 29 2008 7:03 AM

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    Etch Width Assignment Reply

    Hi While routing the design, I want to assign etch width of 0.2mm for particular package symbol having 48 pins & for rest of the design I want to set minimum etch width as 0.3mm. One way I think to assign pin level property but don't know which one. Thanks in advance


    Originally posted in cdnusers.org by Rajiv
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  • Tue, Jan 29 2008 8:41 AM

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    RE: Etch Width Assignment Reply

    There is a couple ways of controlling the etch width automatically:

    1.) You can define a Constraint Area around the component and specify that the etch width in that region to be .2mm.

    If you are using Allegro prior to SPB 16.0 the Constraint Area etch width will be applied thru all layers of the design just make sure to update the Physical Assignment table to call out the .2mm Constraints Set for the Constraint Area. This can be a pain because you may only want the etch width reduced on the external layer where the 48 pin component is placed

    If you are using Allegro SPB 16.0 and above you would define a Constraints Region on the Top Layer and just specify the etch width in Constraints Manager under the Physical Section in the Region worksheet tab.

    2.) If you are planning on manually pin escaping this 48 pin component you change your Physical Neck Width to .2mm and the Line Width to .3mm to avoid any DRC Errors (You would also need to specify a Max Neck Length as well). You can temporarily change your Line Width from .3mm to .2mm then pin escape the 48 pin component then change it back to .3mm when you are done.

    Recommendations:
    If you are using Allegro prior to SPB 16.0 I would use step 2 above.
    If you are using Allegro SPB 16.0 and above I would use step 1 above.

    Hope this helps,
    Mike Catrambone
    UTStarcom, Inc.


    Originally posted in cdnusers.org by mcatramb91
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  • Tue, Jan 29 2008 2:34 PM

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    RE: Etch Width Assignment Reply

    Hi Mike,

    Actually for Option 1, using v15 (.1,.5,.7) and some time back, you can define the constraints area to adhere to all the 'other layer' properties (.3mm), and only set the Top Layer to something different (.2mm). I'd do it by copying the DEFAULT constraint (.3mm) and having a "BREAKOUT" physical property with Top Layer at .2mm. This will route from the device (constraint) area at .2mm width, then change to .3mm beyond the area.

    I do this with my BGA that route out of my constraint with .1mm, then changes to .125mm once I'm beyond the BGA breakout. I can set my internal layers to anything else, if I want, by mod'ing the PHYSICAL CONSTRAINTS.

    Good day.
    Mitch


    Originally posted in cdnusers.org by cadpro2k
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  • Wed, Jan 30 2008 7:13 AM

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    RE: Etch Width Assignment Reply

    Mitch,

    This is very true, that you can modify your .2mm physical constraints set so it just has the modified etch width for the Top Side. The point I was trying to make is that Constraint Areas are defined thru all layers for the designs prior to SPB 16.0 while in SPB 16.0 you can simply define a Constraint Region > Top then assign rules to it and never have to worry about what happens on any other layers.

    Mike


    Originally posted in cdnusers.org by mcatramb91
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Started by archive at 29 Jan 2008 07:03 AM. Topic has 3 replies.