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 uVia on pad 

Last post Wed, Dec 5 2007 7:15 AM by archive. 3 replies.
Started by archive 05 Dec 2007 07:15 AM. Topic has 3 replies and 1141 views
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  • Wed, Dec 5 2007 7:15 AM

    • archive
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    uVia on pad Reply

    Hi all, I have a BGA with a uVia on its pad, and have set under Setup -> Constraints -> Set Values.. "Pad/pad direct connect" to "All Allowed" but a DRC error on pad saying " Top, minimum Blind/Buried Via Stagger distance " appears (see attached image). Does anybody know how to configure the tool to avoid this, without changing the "Min BBvia stagger" option to null? I guess the PCB editor thinks that the uVia on pad is a short, and then flags that DRC error. Thank's in advance, Regards.


    Originally posted in cdnusers.org by luissito
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  • Wed, Dec 5 2007 10:26 AM

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    RE: uVia on pad Reply

    Do you have a spacing or constriant area rule set to this net?

    If you do, make sure your tables are set correctly.

    Good Luck,

    Oscar Miguelino


    Originally posted in cdnusers.org by oscar@oqo.com
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  • Thu, Dec 6 2007 6:23 AM

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    RE: uVia on pad Reply

    Set min "BB via gap" under spacing rule and don't define the same for "Min BBvia Stagger" under physical rule but you can set "Max BBvia Stagger" rule.

    Regards,
    Satya


    Originally posted in cdnusers.org by satya1234
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  • Mon, Dec 10 2007 1:40 AM

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    RE: uVia on pad Reply

    Ok, so as I understand, I have to set "BB via gap" to whatever value I want (depending on the routing class) and "Min BBvia Stagger" to "0" to avoid the DRC's of via on pad's, do I?

    Thanks,
    Luis.


    Originally posted in cdnusers.org by luissito
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Started by archive at 05 Dec 2007 07:15 AM. Topic has 3 replies.