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 How to setup design rules for one chip? 

Last post Tue, Nov 27 2007 4:52 PM by archive. 2 replies.
Started by archive 27 Nov 2007 04:52 PM. Topic has 2 replies and 963 views
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  • Tue, Nov 27 2007 4:52 PM

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    How to setup design rules for one chip? Reply

    Allegro version is 15.7.

    One chip(U1, mcu) 's design rule is different from the rest circuit,
    now i want to setup a design rule for U1(pin to pin : 10mil),
    how to setup it in constraints menu.
    the more detailed, the better.

    thanks in advance.


    Originally posted in cdnusers.org by watchdog1976
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  • Tue, Nov 27 2007 8:57 PM

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    RE: How to setup design rules for one chip? Reply

    Why don't you use area constraint property.
    Have one area for U1.Create separate class under physical and spacingconstraint properties.Attach these to are property.
    Regards,
    Satya


    Originally posted in cdnusers.org by satya1234
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  • Sun, Dec 2 2007 11:52 PM

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    RE: How to setup design rules for one chip? Reply

    good suggestion, thanks


    Originally posted in cdnusers.org by watchdog1976
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Started by archive at 27 Nov 2007 04:52 PM. Topic has 2 replies.