Hi Everybody,Originally posted in cdnusers.org by sriramssr
I am facing some problem with the copper pour in the outer layers. I have done Fan out for SMT components (small trace with via). The GND via will be connected to the inner layer plane.
When i flood the GND copper in the outer layer, i am getting somany "line to via" spacing DRC errors. I could able to clear these erros by touching the trace.
But if i want to modify the outer layer copper shape at any small corner, the same number of DRC errors are repeating.
I have attached PDF snap shot of the same error.
I request your expertise and need solution.
Thanks in advance.