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 DRC Errors with Copper pour 

Last post Thu, Aug 23 2007 4:39 AM by archive. 0 replies.
Started by archive 23 Aug 2007 04:39 AM. Topic has 0 replies and 430 views
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  • Thu, Aug 23 2007 4:39 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
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    DRC Errors with Copper pour Reply

    Hi Everybody,

    I am facing some problem with the copper pour in the outer layers. I have done Fan out for SMT components (small trace with via). The GND via will be connected to the inner layer plane.
    When i flood the GND copper in the outer layer, i am getting somany "line to via" spacing DRC errors. I could able to clear these erros by touching the trace.

    But if i want to modify the outer layer copper shape at any small corner, the same number of DRC errors are repeating.
    I have attached PDF snap shot of the same error.

    I request your expertise and need solution.

    Thanks in advance.
    Sriram


    Originally posted in cdnusers.org by sriramssr
    • Post Points: 0
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Started by archive at 23 Aug 2007 04:39 AM. Topic has 0 replies.