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 Thermal Pad Shape with vias 

Last post Fri, Aug 3 2007 12:19 AM by archive. 2 replies.
Started by archive 03 Aug 2007 12:19 AM. Topic has 2 replies and 1533 views
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  • Fri, Aug 3 2007 12:19 AM

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    Thermal Pad Shape with vias Reply

    Hi, I have two TPS65023 on top layer, these chips have a PowerPad which I defined during symbol making as shapes on ETCH/TOP. In the board I have attached these PowerPads to GND net and my question is... Is there a smart way for fanout these shapes to GND plane or how to connect these shapes to a GND plane which is in an inner layer? I have defined the corresponding blind via from TOP to GND plane. Thank's in advance. Regards.


    Originally posted in cdnusers.org by luissito
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  • Fri, Aug 3 2007 7:18 AM

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    RE: Thermal Pad Shape with vias Reply

    I have used these types of components (QFN with Thermal Pad) at lot over the past couple of years. I add the PowerPad to the package symbol as four separate pins which form the one pad. The reason for this is because TI, among many other vendors, that use these packages recommends that four separate solder paste areas are used in the PowerPad area. To connect down to the GND planes I add vias inside the PowerPad area in the package symbol to immediately connect to planes once placed. I would strongly recommend you review the THERMAL INFORMATION section of the TI Spec sheet and also the TI QFN Application Report which gives you details on the solder pad and solder paste footprint requirements. Attached to this post is an example of one of our QFN footprints which use a PowerPAD underneath the device. Underneath the device there is 5 vias shown as donuts because I have plated holes displayed, 4 top side smd pads which touch each other with stepped back solder paste apertures which space in between each. Hope this help, Mike Catrambone UTStarcom, Inc.


    Originally posted in cdnusers.org by mcatramb91
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  • Mon, Aug 20 2007 4:59 AM

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    RE: Thermal Pad Shape with vias Reply

    Thank you very much Mike, and sorry for the late feedback as I was on holiday. I am going to modify the symbol at library level as you mention and by the way what kind of via do you use in the thermal pad, I need them to be blind ones but instead of defined them as blind ones in the padstack designer I do it in the PCB editor with a kind of assistant in order to generate blind vias from TOP (thermal pad) to all possible internal GND planes, is that the right way? Regards.


    Originally posted in cdnusers.org by luissito
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Started by archive at 03 Aug 2007 12:19 AM. Topic has 2 replies.