Hi Originally posted in cdnusers.org by BillZ_EMA
I was wondering how some of you handle FPGA's in your HDL to Allegro flow. Specifically how you hand the pin and gate swapping and backannotate that to your fpga tool. Is anyone using custom skill or perl scripts?
I would be curios to hear from anyone how they deal with this and also how important this process is to your process.
EMA Design Automation