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 Backaanotaion of pin swaps for fpga's 

Last post Wed, May 16 2007 1:33 PM by archive. 0 replies.
Started by archive 16 May 2007 01:33 PM. Topic has 0 replies and 452 views
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  • Wed, May 16 2007 1:33 PM

    • archive
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    Backaanotaion of pin swaps for fpga's Reply

    Hi
    I was wondering how some of you handle FPGA's in your HDL to Allegro flow. Specifically how you hand the pin and gate swapping and backannotate that to your fpga tool. Is anyone using custom skill or perl scripts?

    I would be curios to hear from anyone how they deal with this and also how important this process is to your process.

    Thank You
    BillZ
    EMA Design Automation


    Originally posted in cdnusers.org by BillZ_EMA
    • Post Points: 0
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Started by archive at 16 May 2007 01:33 PM. Topic has 0 replies.